Health Score

0 Excellent

Metadata coverage

Abstract

ORCID

References

License

Extended metadata coverage

Informational — signals of interoperability and funding across the corpus. Not part of the health score.

Funding

Funder

Award / grant

Affiliation & institutional identifiers

Affiliation

ROR ID

Update policy

Your prioritized action plan

Ordered by how many DOIs each fix touches — start here, not with every error at once.

Attach ORCID iDs across 173 articles

ORCID iDs strengthen author disambiguation and institutional reporting.

Medium impact173 DOIs

Deposit reference lists for 12 records

Deposited references power Crossref's Cited-by links between your articles and the literature.

Low impact12 DOIs

DOIs for this ISSN

Showing the top 5 of 597 DOIs, ordered by correction priority.

#	Title	Missing	Priority	Citations
1	An Open-Source Tool Set Enabling Analog-Digital-Software Co-… (10.3390/jlpea6010003)	ORCID	42.03	47
2	A Survey of Neural Front End Amplifiers and Their Requiremen… (10.3390/jlpea4040268)	ORCID	40.58	41
3	Low Power Design for Future Wearable and Implantable Devices (10.3390/jlpea6040020)	ORCID	40.58	41
4	CMOS Leakage and Power Reduction in Transistors and Circuits… (10.3390/jlpea2010001)	ORCID	40.32	40
5	Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for… (10.3390/jlpea3020054)	ORCID	40.32	40
6	Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design… (10.3390/jlpea1010001)	ORCID	39.49	37
7	Synchronous Counter Design Using Novel Level Sensitive T-FF… (10.3390/jlpea9030027)	ORCID	38.91	35
8	Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low… (10.3390/jlpea5020081)	ORCID	38.60	34
9	Low Power Dendritic Computation for Wordspotting (10.3390/jlpea3020073)	ORCID	37.63	31
10	Compact Modeling Solutions for Oxide-Based Resistive Switchi… (10.3390/jlpea4010001)	ORCID	37.28	30
11	Scaling Floating-Gate Devices Predicting Behavior for Progra… (10.3390/jlpea6030013)	ORCID	37.28	30
12	A Low-Power Hardware-Friendly Binary Decision Tree Classifie… (10.3390/jlpea1010045)	ORCID	36.93	29
13	A Survey of Cache Bypassing Techniques (10.3390/jlpea6020005)	ORCID	36.56	28
14	SoC-Based Edge Computing Gateway in the Context of the Inter… (10.3390/jlpea8010001)	ORCID	36.56	28
15	Inkjet Printed Fully-Passive Body-Worn Wireless Sensors for… (10.3390/jlpea7040026)	ORCID	36.18	27
16	Comprehensive Study of Security and Privacy of Emerging Non-… (10.3390/jlpea11040036)	ORCID	35.78	26
17	Physical, Electrical, and Reliability Considerations for Cop… (10.3390/jlpea8020020)	ORCID	35.78	26
18	On Improving Reliability of SRAM-Based Physically Unclonable… (10.3390/jlpea7010002)	ORCID	35.37	25
19	Design and Analysis of Double-Gate MOSFETs for Ultra-Low Pow… (10.3390/jlpea1020277)	ORCID	34.95	24
20	Analog Architecture Complexity Theory Empowering Ultra-Low P… (10.3390/jlpea9010004)	ORCID	34.95	24
21	Embedded Memory Hierarchy Exploration Based on Magnetic Rand… (10.3390/jlpea4030214)	ORCID	34.04	22
22	Hardware-Efficient Delta Sigma-Based Digital Signal Processi… (10.3390/jlpea5040234)	ORCID	33.56	21
23	A DC-DC Converter Efficiency Model for System Level Analysis… (10.3390/jlpea3030215)	ORCID	33.06	20
24	A Review and Modern Approach to LC Ladder Synthesis (10.3390/jlpea1010020)	ORCID	31.38	17
25	Starting Framework for Analog Numerical Analysis for Energy-… (10.3390/jlpea7030017)	ORCID	31.38	17
26	Three-Dimensional Wafer Stacking Using Cu TSV Integrated wit… (10.3390/jlpea4020077)	ORCID	30.76	16
27	Simple Scheme for the Implementation of Low Voltage Fully Di… (10.3390/jlpea10040034)	ORCID	30.10	15
28	Timing-Error Detection Design Considerations in Subthreshold… (10.3390/jlpea2020180)	ORCID	30.10	15
29	Flexible, Scalable and Energy Efficient Bio-Signals Processi… (10.3390/jlpea7020016)	ORCID	30.10	15
30	Enabling Energy-Efficient Physical Computing through Analog… (10.3390/jlpea8040047)	ORCID	30.10	15
31	Coverage Layout Design Rules and Insertion Utilities for CMP… (10.3390/jlpea11010002)	ORCID	29.40	14
32	Ultra-Low Power Consuming Direct Radiation Sensors Based on… (10.3390/jlpea7030020)	ORCID	29.40	14
33	Radiation Hardened NULL Convention Logic Asynchronous Circui… (10.3390/jlpea5040216)	ORCID	28.65	13
34	A Sub-Threshold 8T SRAM Macro with 12.29 nW/KB Standby Power… (10.3390/jlpea6020008)	ORCID	28.65	13
35	Models and Techniques for Temperature Robust Systems on a Re… (10.3390/jlpea7030021)	ORCID	28.65	13
36	Adaptative Techniques to Reduce Power in Digital Circuits (10.3390/jlpea1020261)	ORCID	27.85	12
37	Hardware Implementation of an Automatic Rendering Tone Mappi… (10.3390/jlpea3040337)	ORCID	27.85	12
38	Study of Back Biasing Schemes for ULV Logic from the Gate Le… (10.3390/jlpea4030168)	ORCID	27.85	12
39	A Technique for Improving Lifetime of Non-Volatile Caches Us… (10.3390/jlpea6010001)	ORCID	27.85	12
40	A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power I… (10.3390/jlpea6020010)	ORCID	27.85	12
41	Extending the Performance of Hybrid NoCs beyond the Limitati… (10.3390/jlpea7020008)	ORCID	27.85	12
42	Tolerating Permanent Faults in the Input Port of the Network… (10.3390/jlpea9010011)	ORCID	27.85	12
43	Data-Driven Approaches for Computation in Intelligent Biomed… (10.3390/jlpea1010150)	ORCID	26.98	11
44	Short-Circuit Power Reduction by Using High-Threshold Transi… (10.3390/jlpea2010069)	ORCID	26.98	11
45	Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V (10.3390/jlpea4020065)	ORCID	26.98	11
46	Delay Insensitive Ternary CMOS Logic for Secure Hardware (10.3390/jlpea5030183)	ORCID	26.98	11
47	A Novel Design Flow for a Security-Driven Synthesis of Side-… (10.3390/jlpea7010004)	ORCID	26.98	11
48	A Case for Security-Aware Design-Space Exploration of Embedd… (10.3390/jlpea10030022)	ORCID	26.03	10
49	A Minimum Leakage Quasi-Static RAM Bitcell (10.3390/jlpea1010204)	ORCID	26.03	10
50	Error Detection and Recovery Techniques for Variation-Aware… (10.3390/jlpea1030334)	ORCID	26.03	10